Special Purpose Computer Architectures for High Speed Optimisation

David Abramson, A de Silva, Marcus Randall, Adam Postula

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

5 Citations (Scopus)

Abstract

This paper discussed two computationally intensive optimisation algorithms for 0-1 integer programs, namely simulated annealing and branch and bound. It then describes an application specific computing platform designed to accelerate their performance. The paper justifies the general approach and gives details of the algorithms
Original languageEnglish
Title of host publicationProceedings of the Second Australasian Conference on Parallel and Real Time Systems
Place of PublicationFremantle
Pages13-20
Number of pages8
Publication statusPublished - Sep 1995
Externally publishedYes

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Computer architecture
Simulated annealing

Cite this

Abramson, D., de Silva, A., Randall, M., & Postula, A. (1995). Special Purpose Computer Architectures for High Speed Optimisation. In Proceedings of the Second Australasian Conference on Parallel and Real Time Systems (pp. 13-20). Fremantle.
Abramson, David ; de Silva, A ; Randall, Marcus ; Postula, Adam. / Special Purpose Computer Architectures for High Speed Optimisation. Proceedings of the Second Australasian Conference on Parallel and Real Time Systems. Fremantle, 1995. pp. 13-20
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Abramson, D, de Silva, A, Randall, M & Postula, A 1995, Special Purpose Computer Architectures for High Speed Optimisation. in Proceedings of the Second Australasian Conference on Parallel and Real Time Systems. Fremantle, pp. 13-20.

Special Purpose Computer Architectures for High Speed Optimisation. / Abramson, David; de Silva, A; Randall, Marcus; Postula, Adam.

Proceedings of the Second Australasian Conference on Parallel and Real Time Systems. Fremantle, 1995. p. 13-20.

Research output: Chapter in Book/Report/Conference proceedingConference contributionResearchpeer-review

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Abramson D, de Silva A, Randall M, Postula A. Special Purpose Computer Architectures for High Speed Optimisation. In Proceedings of the Second Australasian Conference on Parallel and Real Time Systems. Fremantle. 1995. p. 13-20